We know that a Flip-Flop can store a 1 bit of digital information (1 or 0) .It is also referred as 1-bit register. Registers find application in a verity of information in digital systems including microprocessor. For example Intel’s 8085 microprocessor contains seven 8-bit registers and five 1-bit registers.
The data can be entered in serial (1-bit at a time) or in parallel form (all the bits simultaneously) and can be retrieved in serial or parallel form. Data in serial form is called temporal code where as data in parallel form is called special code. A 4-bit data 1010 is shown in fig a) and in parallel form in fig b).
Registers are classified depending upon the way in which the data are entered and retrieved. There are four possible modes of operations:
- Serial-in ,serial-out (SISO)
- Serial-in, parallel-out (SIPO)
- Parallel-in, series-out (PISO)
- Parallel-in, parallel-out (PIPO)
Registers can be designed using various Flip-Flops (S-R or J-K as D-type) and are also available as MSI devices.
Registers in which data are entered or/and taken out in serial form are referred as shift registers, since bits are shifted in the Flip-Flops with the occurrence of clock pulses either in the right direction or in the left direction or in both the directions (Bi-directional). IC74295A is a bi-directional shift register.
A register is referred as universal register if it be operated in all the four possible modes and also as bi-directional registers. For example 74194 is a universal register.
Universal Shift Register:
A universal shift register is a bidirectional register, whose input can either in serial form or in parallel form and whose output can also be either in serial form or in parallel form.
Following figure shows the logic diagram of the 74194 4-bit universal shift register. Note that the output of each flip flop is routed through AOI logic to the stage on its right and to the stage on its left. The mode control inputs S0, and S1, are used to enable the left to, right connections when it is desired to shift-right, and the right-to-left connections when it is desired to shift-left.
The truth table shows that no shifting occurs when S0 and S1 are either LOW or both HIGH. When So = S1=0, there is no change in the contents of the register, and when So = S1 = 1, the parallel input data A, B, C and D are loaded into the register on the rising edge of the clock pulse. The combination S0 = S1= 0, is said to inhibit the loading of serial or parallel data, since the register contents cannot change under that condition. The register has an asynchronous active-Low clear input, which can be used to reset all the flip flops irrespective of the clock and any serial or parallel inputs.
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